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1 ? february, 2003 HIP4081 80v/2.5a peak, high frequency full bridge fet driver the HIP4081 is a high frequency, medium voltage full bridge n-channel fet driver ic, available in 20 lead plastic soic and dip packages. the HIP4081 can drive every possible switch combination except those which would cause a shoot-through condition . the HIP4081 can switch at frequencies up to 1mhz and is well suited to driving voice coil motors, high-frequency switching power amplifiers, and power supplies. for example, the HIP4081 c an drive medium voltage brush motors, and two HIP4081s can be used to drive high performance stepper motors, since the short minimum ?on-time? can provide fine micro-stepping capability. short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in rapid, precise control of the driven load. a similar part, the hip4080, includes an on-chip input comparator to create a pwm sig nal from an external triangle wave and to facilitate ?hysteresis mode? switching. see application note an9325 for HIP4081, document #9325. intersil web home page: http://www.intersil.com similar part HIP4081a includes undervoltage circuitry which does not require the circuitry shown in figure 30 of this data sheet. pinout features ? independently drives 4 n-channel fet in half bridge or full bridge configurations ? bootstrap supply max voltage to 95v dc ? drives 1000pf load at 1mhz in free air at 50 o c with rise and fall times of typically 10ns ? user-programmable dead time ? on-chip charge-pump and bootstrap upper bias supplies ? dis (disable) overrides input control ? input logic thresholds compatible with 5v to 15v logic levels ? very low power consumption applications ? medium/large voice coil motors ? full bridge power supplies ? switching power amplifiers ? high performance motor controls ? noise cancellation systems ? battery powered vehicles ? peripherals ?u.p.s. 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb bhi dis v ss bli ali hdel ahi ldel ahb bho blo bls v dd bhs v cc als alo ahs aho HIP4081 (20-lead pdip, soic) top view ordering information part number temp. range ( o c) package pkg. no. HIP4081ip -40 to 85 20 lead plastic dip e20.3 HIP4081ib -40 to 85 20 lead plastic soic m20.3 data sheet fn3556.9 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners. n o t r e c o m m e n d e d f o r n e w d e s i g n s p o s s i b l e s u b s t i t u t e p r o d u c t i n t e r s i l p a r t n u m b e r h i p 4 0 8 1 a
2 application block diagram functional block diagram (1/2 HIP4081) 80v gnd HIP4081 gnd 12v load ahi ali bli bhi blo bhs bho alo ahs aho charge pump v dd ahi dis ali hdel ldel v ss turn-on delay turn-on delay driver driver ahb aho ahs v cc alo als c bf to v dd (pin 16) c bs d bs high voltage bus 80v dc +12v dc level shift and latch 14 10 11 12 15 13 16 7 3 6 8 9 4 bias supply HIP4081 HIP4081
3 typical application (p wm mode switching) 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb bhi dis v ss bli ali hdel ahi ldel ahb bho blo bls v dd bhs v cc als alo ahs aho 80v 12v + - 12v dis gnd 6v gnd to optional current controller pwm load input HIP4081 HIP4081
4 absolute maximum rati ngs thermal information (typical, note 1) supply voltage, v dd and v cc . . . . . . . . . . . . . . . . . . . .-0.3v to 16v logic i/o voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v voltage on ahs, bhs . . . -6.0v (transient) to 80v (25 o c to 125 o c) voltage on ahs, bhs . . -6.0v (transient) to 70v (-55 o c to 125 o c) voltage on als, bls . . . . . . . -2.0v (transient) to +2.0v (transient) voltage on ahb, bhb . . . . . . v ahs, bhs -0.3v to v ahs, bhs +16v voltage on alo, blo. . . . . . . . . . . . v als, bls -0.3v to v cc +0.3v voltage on aho, bho . . . . . .v ahs, bhs -0.3v to v ahb, bhb +0.3v input current, hdel and ldel . . . . . . . . . . . . . . . . . . -5ma to 0ma phase slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v/ns all voltages are relative to pin 4, v ss , unless otherwise specified. storage temperature range . . . . . . . . . . . . . . . . . . -65 o c to 150 o c operating max. junction temperature . . . . . . . . . . . . . . . . . . 125 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300 o c (for soic - lead tips only) thermal resistance, junction-ambient soic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 o c/w dip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 o c/w operating conditions supply voltage, v dd and v cc . . . . . . . . . . . . . . . . . . . .+6v to +15v voltage on als, bls . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to +1.0v voltage on ahb, bhb . . . . . . . v ahs, bhs +5v to v ahs, bhs +15v input current, hdel and ldel . . . . . . . . . . . . . . . .-500 a to -50 a operating ambient temperature range . . . . . . . . . . -40 o c to 85 o c caution: stresses above those listed in ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other condi tions above those indicated in the operational se ctions of this specification is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k and t a =25 o c, unless otherwise specified parameter symbol test conditions t j = 25 o c t js = -40 o c to 125 o c units min typ max min max supply currents and charge pumps v dd quiescent current i dd all inputs = 0v 7 9 11 6 12 ma v dd operating current i ddo outputs switching f = 500khz 8 9.5 12 7 13 ma v cc quiescent current i cc all inputs = 0v, i alo = i blo = 0 - 0.1 10 - 20 a v cc operating current i cco f = 500khz, no load 1 1.25 2.0 0.8 3 ma ahb, bhb quiescent current - qpump output current i ahb , i bhb all inputs = 0v, i aho = i bho = 0 v dd = v cc = v ahb = v bhb = 10v -50 -30 -15 -60 -10 a ahb, bhb operating current i ahbo , i bhbo f = 500khz, no load 0.5 0.9 1.3 0.4 1.7 ma ahs, bhs, ahb, bhb leakage current i hlk v ahs = v bhs = v ahb = v bhb = 95v - 0.02 1.0 - 10 a ahb-ahs, bhb-bhs qpump output voltage v ahb -v ahs v bhb -v bhs i ahb = i ahb = 0, no load 11.5 12.6 14.0 10.5 14.5 v input pins: ali, bli, ahi, bhi, and dis low level input voltage v il full operating conditions - - 1.0 - 0.8 v high level input voltage v ih full operating conditions 2.5 - - 2.7 - v input voltage hysteresis -35- - - mv low level input current i il v in = 0v, full operating conditions -130 -100 -75 -135 -65 a high level input current i ih v in = 5v, full operating conditions -1 - +1 -10 +10 a turn-on delay pins: ldel and hdel ldel, hdel voltage v hdel, v ldel i hdel = i ldel = -100 a 4.9 5.1 5.3 4.8 5.4 v gate driver output pins: alo, blo, aho, and bho low level output voltage v ol i out = 100ma 0.7 0.85 1.0 0.5 1.1 v high level output voltage v cc -v oh i out = -100ma 0.8 .95 1.1 0.5 1.2 v HIP4081 HIP4081
5 peak pullup current i o +v out = 0v 1.7 2.6 3.8 1.4 4.1 a peak pulldown current i o -v out = 12v 1.7 2.4 3.3 1.3 3.6 a electrical specifications v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k and t a =25 o c, unless otherwise specified (continued) parameter symbol test conditions t j = 25 o c t js = -40 o c to 125 o c units min typ max min max switching specifications v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 10k, c l = 1000pf parameter symbol test conditions t j = +25 o c t js = 40 o c to 125 o c units min typ max min max lower turn-off propagation delay (ali-alo, bli-blo) t lphl -3060-80ns upper turn-off propagation delay (ahi-aho, bhi-bho) t hphl -3570-90ns lower turn-on propagation delay (ali-alo, bli-blo) t lplh -4570-90ns upper turn-on propagation delay (ahi-aho, bhi-bho) t hplh - 60 90 - 110 ns rise time t r -1025-35ns fall time t f -1025-35ns turn-on input pulse width t pwin-on 50 - - 50 - ns turn-off input pulse width t pwin-off 40 - - 40 - ns disable turn-off propagation delay (dis - lower outputs) t dislow -4575-95ns disable turn-off propagation delay (dis - upper outputs) t dishigh - 55 85 - 105 ns disable to lower turn-on propagation delay (dis - alo and blo) t dlplh -3570-90ns refresh pulse width (alo and blo) t ref-pw 160 260 380 140 420 ns disable to upper enable (dis - aho and bho) t hen - 335 500 - 550 ns truth table input output ali, bli ahi, bhi dis alo, blo aho, bho xx1 0 0 1x0 1 0 010 0 1 000 0 0 note: x signifies that input can be either a ?1? or ?0?. HIP4081 HIP4081
6 pin descriptions pin number symbol description 1 bhb b high-side bootstrap supply. external bootstrap di ode and capacitor are required. connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. internal charge pump supplies 30 a out of this pin to maintain bootstrap supply. internal ci rcuitry clamps the bootstrap supply to approximately 12.8v. 2 bhi b high-side input. logic level input that controls bho driver (pin 20). bli (pin 5) high level input overrides bhi high level input to prevent half-bridge shoot-through, see truth t able. dis (pin 3) high level input overrides bhi high level input. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). 3 dis disable input. logic level input that when taken high sets all four outputs low. dis high overrides all other inputs. when dis is taken low the outputs are controlled by the other inputs. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). 4v ss chip negative supply, gener ally will be ground. 5 bli b low-side input. logic level input that controls blo driver (pin 18). if bhi (pin 2) is driven high or not connected externally then bli controls both blo and bho drivers, wi th dead time set by delay currents at hdel and ldel (pin 8 and 9). dis (pin 3) high level input overrides bli high le vel input. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). 6 ali a low-side input. logic level input that controls alo driver (pin 13). if ahi (pin 7) is driven high or not connected externally then ali controls both alo and aho drivers, wi th dead time set by delay currents at hdel and ldel (pin 8 and 9). dis (pin 3) high level input overrides ali high le vel input. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). 7 ahi a high-side input. logic level input that controls aho driver (pin 11). ali (pin 6) high level input overrides ahi high level input to prevent half-bridge shoot-through, see truth t able. dis (pin 3) high level input overrides ahi high level input. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). 8 hdel high-side turn-on delay. connec t resistor from this pin to v ss to set timing current that defines the turn-on delay of both high-side drivers. the low-side drivers turn-off with no adjustable delay, so the hdel resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. hdel reference vo ltage is approximately 5.1v. 9 ldel low-side turn-on delay. connect resistor from this pin to v ss to set timing current that defines the turn-on delay of both low-side drivers. the high-side drivers turn-off with no adjustable delay, so the ldel resistor guarantees no shoot-through by delaying the turn-on of the low-side dr ivers. ldel reference voltage is approximately 5.1v. 10 ahb a high-side bootstrap supply. external bootstrap di ode and capacitor are required. connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. internal charge pump supplies 30 a out of this pin to maintain bootstrap supply. internal ci rcuitry clamps the bootstrap supply to approximately 12.8v. 11 aho a high-side output. connect to gate of a high-side power mosfet. 12 ahs a high-side source connection. connect to source of a high-side power mosfet. connect negative side of bootstrap capacitor to this pin. 13 alo a low-side output. connect to gate of a low-side power mosfet. 14 als a low-side source connection. connect to source of a low-side power mosfet. 15 v cc positive supply to gate drivers. must be same potential as v dd (pin 16). connect to anodes of two bootstrap diodes . 16 v dd positive supply to lower gate driver s. must be same potential as v cc (pin 15). de-couple this pin to v ss (pin 4). 17 bls b low-side source connection. connect to source of b low-side power mosfet. 18 blo b low-side output. connect to gate of b low-side power mosfet. 19 bhs b high-side source connection. connect to source of b high-side power mosfet. connect negative side of bootstrap capacitor to this pin. 20 bho b high-side output. connect to gate of b high-side power mosfet. HIP4081 HIP4081
7 timing diagrams figure 1. independent mode figure 2. bistate mode figure 3. disable function dis = 0 xli xhi xlo xho t lphl t hphl t hplh t lplh t r (10% - 90%) t f (10% - 90%) x = a or b, a and b halves of bridge controller are independent dis = 0 xli xhi = hi or not connected xlo xho dis xli xhi xlo xho t dlplh t dis t hen t ref-pw HIP4081 HIP4081
8 typical performance curves v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k and t a = 25 o c, unless otherwise specified figure 4. quiescent i dd supply current vs v dd supply voltage figure 5. i ddo , no-load i dd supply current vs frequency (khz) figure 6. side a, b floating supply bias current vs frequency (load = 1000pf) figure 7. i cco , no-load i cc supply current vs frequency (khz) temperature figure 8. i ahb , i bhb no-load floating supply current vs frequence figure 9. ali, bli, ahi, bhi low level input current i il vs temperature 6 8 10 12 14 2.0 4.0 6.0 8.0 10.0 12.0 14.0 i dd supply current (ma) v dd supply voltage (v) 0 100 200 300 400 500 600 700 800 900 1000 8.0 8.5 9.0 9.5 10.0 10.5 11.0 supply current (ma) switching frequency (khz) 0 100 200 300 400 500 600 700 800 900 1000 0.0 5.0 10.0 15.0 20.0 25.0 30.0 floating supply bias current (ma) switching frequency (khz) 0 100 200 300 400 500 600 700 800 900 1000 0.0 1.0 2.0 3.0 4.0 5.0 i cc supply current (ma) switching frequency (khz) 75 o c 25 o c 125 o c -40 o c 0 o c 0 200 400 600 800 1000 -0.2 0.2 0.6 1.0 1.4 1.8 floating supply bias current (ma) switching frequency (khz) -50 -25 0 25 50 75 100 125 -120 -110 -100 -90 low level input current ( a) junction temperature ( o c) HIP4081 HIP4081
9 figure 10. ahb - ahs, bhb - bhs no-load charge pump voltage vs temperature figure 11. upper disable turn-off pr opagation delay t dishigh vs temperature figure 12. disable to upper enable t uen propagation delay vs temperature figure 13. disable to upper enable t uen propagation delay vs temperature figure 14. t ref-pw refresh pulse width vs temperature figure 15. disable to lower enable t dlplh propagation delay vs temperature typical performance curves v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k and t a = 25 o c, unless otherwise specified (continued) -40 -20 0 20 40 60 80 100 120 10.0 11.0 12.0 13.0 14.0 15.0 no-load floating charge pump junction temperature ( o c) voltage (v) -40 -20 0 20 40 60 80 100 120 30 40 50 60 70 80 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 300 320 340 360 380 400 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 30 40 50 60 70 80 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 175 225 275 325 375 refresh pulse width (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 20 30 40 50 60 70 80 propagation delay (ns) junction temperature ( o c) HIP4081 HIP4081
10 figure 16. upper turn-off propagation delay t hphl vs temperature figure 17. upper turn-o n propagation delay t hplh vs temperature figure 18. lower turn-off propagation delay t lphl vs temperature figure 19. lower turn-on propagation delay t lplh vs temperature figure 20. gate drive fall time t f vs temperature figure 21. gate drive rise time t r vs temperature typical performance curves v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k and t a = 25 o c, unless otherwise specified (continued) -40 -20 0 20 40 60 80 100 120 20 30 40 50 60 70 80 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 20 30 40 50 60 70 80 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 20 30 40 50 60 70 80 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 20 30 40 50 60 70 80 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 8.5 9.5 10.5 11.5 12.5 13.5 gate drive fall time (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 8.5 9.5 10.5 11.5 12.5 13.5 turn-on rise time (ns) junction temperature ( o c) HIP4081 HIP4081
11 figure 22. v ldel , v hdel voltage vs temperature figure 23. high level outp ut voltage v cc - v oh vs bias supply and temperature at 100ma figure 24. low level output voltage v ol vs bias supply and temperture at 100ma figure 25. peak pulldown current i o vs bias supply voltage figure 26. peak pullup current i o+ vs bias supply voltage figure 27. low voltage bias current i dd (less quiescent component) vs frequency and gate load capacitance typical performance curves v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k and t a = 25 o c, unless otherwise specified (continued) -40 -20 0 20 40 60 80 100 120 4.0 4.5 5.0 5.5 6.0 hdel, ldel input voltage (v) junction temperature ( o c) 6 8 10 12 14 0 250 500 750 1000 1250 1500 v cc - v oh (mv) bias supply voltage (v) 75 o c 25 o c 125 o c -40 o c 0 o c 6 8 10 12 14 0 250 500 750 1000 1250 1500 v ol (mv) bias supply voltage (v) 75 o c 25 o c 125 o c -40 o c 0 o c 6 7 8 9 10 11 12 13 14 15 16 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 gate drive sink current (a) v dd , v cc , v ahb , v bhb (v) 6 7 8 9 10 11 12 13 14 15 16 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 gate drive sink current (a) v dd , v cc , v ahb , v bhb (v) 1 10 100 1000 2 5 20 50 500 200 0.1 1 10 100 500 50 5 0.5 200 20 2 0.2 low voltage bias current (ma) switching frequency (khz) 100pf 1,000pf 10,000pf 3,000pf HIP4081 HIP4081
12 hi4081 power-up application information the HIP4081 h-bridge driver ic requires external circuitry to assure reliable start-up conditions of the upper drivers. if not addressed in the application, the h-bridge power mosfets may be exposed to shoot-through current, possibly leading to mosfet failure. followin g the instructions below will result in reliable start-up. the HIP4081 has four inputs, one for each output. outputs alo and blo are directly controlled by input ali and bli. by holding ali and bli low during start-up no shoot-through conditions can occur. to set the latches to the upper drivers such that the driver outputs, aho and bho, are off, the dis pin must be toggled from low to high after power is applied. this is accomplished with a simp le resistor divider, as shown below in figure 30. as the v dd /v cc supply ramps from zero up, the dis voltage is below its input threshold of 1.7v due to the r1/r2 resistor divider. when v dd /v cc exceeds approximately 9v to 10v, dis becomes greater than the input threshold and the chip disables all outputs. it is critical that ali and bli be held low prior to dis reaching its threshold level of 1.7v while v dd /v cc is ramping up, so that shoot through is avoided. after power is up the chip can be enabled by the enable signal which pulls the dis pin low. figure 28. high voltage level-shift current vs frequency and bus voltage figure 29. minimum dead-time vs del resistance typical performance curves v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k and t a = 25 o c, unless otherwise specified (continued) 1 10 100 1000 2 5 20 50 200 500 1 10 100 1000 2 5 20 50 200 500 level-shift current ( a) switching frequency (khz) 60v 40v 80v 20v 10 50 100 150 200 250 0 30 60 90 120 150 hdel/ldel resistance (k ? ) dead-time (ns) 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb bhi dis v ss bli ali hdel ahi ldel ahb bho blo bls v dd bhs v cc als alo ahs aho 3.3k r2 enable r1 15k figure 30a. v dd dis ali, bli t1 8.5v to 10.5v (assumes 5% resistors) 1.7v 12v, final value notes: 2. ali and/or bli may be high after t1, whereupon the enable pin may also be brought high. 3. another product, HIP4081a, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry. figure 30b. timing diagram for figure 30a HIP4081 HIP4081
13 HIP4081 1 2 3 1 2 3 1 2 3 6 5 1 2 3 2 1 12 13 1 2 3 10 11 1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 l1 r21 q1 q3 q4 r22 l2 r23 c1 c3 jmpr1 r24 r30 r31 c2 r34 c4 cr2 cr1 q2 jmpr5 jmpr3 jmpr2 jmpr4 r33 c5 c6 cx cy c8 u1 cw cw + b+ in2 in1 bo out/bli in-/ahi com in+/ali +12v +12v bls ao hen/bhi als cd4069ub cd4069ub cd4069ub cd4069ub hip4080/81 section control logic power section driver section r29 u2 u2 u2 u2 4 3 8 9 r32 i o o cd4069ub cd4069ub to dis pin 15k 3.3k enable in u2 u2 aho ahb ahs ldel alo hdel als in-/ahi v cc in+/ali v dd out/bli bls v ss blo dis bhs hen/bhi bho bhb notes: 4. device cd4069ub pin 7 = com, pin 14 = +12v. 5. components l1, l2, c1, c2, cx, cy, r30, r31, not supplied. refe r to application note for description of input logic operation to determine jumper locations for jmpr1 - jmpr4. figure 31. HIP4081 evaluation board schematic HIP4081
14 HIP4081 r22 1 q3 l1 c1 jmpr2 jmpr5 r31 r33 cr2 r23 r24 r27 r28 r26 1 q4 1 q2 jmpr3 u1 r21 gnd l2 c3 c2 c4 jmpr4 jmpr1 r30 cr1 u2 r34 bo ao r32 i o c8 r29 c7 c6 c5 cy cx 1 q1 com +12v b+ in1 in2 aho bho alo blo bls bls ldel hdel dis als als o + + hip4080/81 figure 32. HIP4081 evaluation board silkscreen HIP4081
15 supplemental information for hip4080 and HIP4081 power application the hip4080 and HIP4081 h-bridge driver ics require external circuitry to assure re liable start-up conditions of the upper drivers. if not addressed in the application, the h-bridge power mosfets may be exposed to shoot- through current, possibly leading to mosfet failure. following the instructions below will result in reliable start- up. HIP4081 the HIP4081 has four inputs, one for each output. outputs alo and blo are directly controlled by input ali and bli. by holding ali and bli low during start-up no shoot-through conditions can occur. to set the latches to the upper drivers such that the driver outputs, aho and bho, are off, the dis pin must be toggled from low to high after power is applied. this is accomplished with a simp le resistor divider, as shown below in figure 33. as the v dd /v cc supply ramps from zero up, the dis voltage is below its in put threshold of 1.7v due to the r1/r2 resistor divider. when v dd /v cc exceeds approximately 9v to 10v, dis becomes greater than the input threshold and the chip disables all outputs. it is critical that ali and bli be held low prior to dis reaching its threshold level of 1.7v while v dd /v cc is ramping up, so that shoot through is avoided. after power is up the chip can be enabled by the enable signal which pulls the dis pin low. hip4080 the hip4080 does not have an input protocol like the HIP4081 that keeps both lower power mosfets off other than through the dis pin. in+ and in- are inputs to a comparator that control the bridge in such a way that only one of the lower power devices is on at a time, assuming dis is low. however, keeping both lower mosfets off can be accomplished by controlling the lower turn-on delay pin, ldel, while the chip is enabled, as shown in figure 34. pulling ldel to v dd will indefinitely delay the lower turn-on delays through the input compar ator and will keep the lower mosfets off. with the lower mosfets off and the chip enabled, i.e., dis = low, in+ or in- can be switched through a full cycle, properly setting t he upper driver outputs. once this is accomplished, ldel is released to its normal operating point. it is critical that in+/in- switch a full cycle while ldel is held high, to avoid shoot-through. this start- up procedure can be initiated by the supply voltage and/or the chip enable command by the circuit in figure 33. figure 33. figure 34. 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb bhi dis v ss bli ali hdel ahi ldel ahb bho blo bls v dd bhs v cc als alo ahs aho 3.3k r2 enable r1 15k 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb bhi dis v ss bli ali hdel ahi ldel ahb bho blo bls v dd bhs v cc als alo ahs aho 3.3k r2 r1 15k enable 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb hen dis v ss out in+ hdel in- ldel ahb bho blo bls v dd bhs v cc als alo ahs aho 100k rdel rdel v dd 0.1 f 2n3906 v dd enable v dd 56k 8.2v 56k 100k HIP4081 HIP4081
16 timing diagrams note: 6. ali and/or bli may be high after t1, whereupon the enable pin may also be brought high. figure 35. note: 7. between t1 and t2 the in+ and in- inputs must cause the out pin to go through one complete cycle (transition order is not important). if the enable pin is low after the undervoltage circuit is satisfied, the enable pin will initiate the 10ms time delay during which the in+ and in- pins must cycle at least once. figure 36. v dd dis ali, bli 8.5v to 10.5v (assumes 5% resistors) 1.7v 12v, final value v dd dis ldel =10ms t1 t2 8.3v to 9.1v (assumi ng 5% zener tolerance) 12v, final value 5.1v HIP4081 HIP4081
17 HIP4081 e20.3 (jedec ms-001-ad issue d) 20 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.55 1.77 8 c 0.008 0.014 0.204 0.355 - d 0.980 1.060 24.89 26.9 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n20 209 rev. 0 12/93 notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or prot rusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendicular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m b s e a -c- dual-in-line plastic packages (pdip) HIP4081
18 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HIP4081 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m20.3 (jedec ms-013-ac issue c) 20 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.4961 0.5118 12.60 13.00 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n20 207 0 o 8 o 0 o 8 o - rev. 0 12/93 small outline plast ic packages (soic) HIP4081

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